Symposium X—MRS/The Kavli Foundation Frontiers of Materials

Suman Datta, Georgia Institute of Technology

Plenty of Room at the Top and Bottom

Written by Alison Hatt

In Thursday’s Symposium X symposium, Suman Datta took the audience through two decades of his work on transistor technologies and highlighted some formidable challenges currently on the horizon. His talk was titled, “Plenty of room at the top and bottom,” and he stressed that early-career scientists entering the field today will still find ample research opportunities for decades to come. “No matter what you hear in the press about things coming to an end,” he said, “the semiconductor industry is actually pretty healthy.”

When Datta’s career was starting in the early 2000s, the semiconductor industry was in the era of “geometric scaling,” continually reducing the dimensions and operating voltages of transistors in order to improve performance and fit ever more transistors on a chip. In his early work at Intel, Datta and colleagues brought transistor dimensions down almost to single-digit nanometer scales, developing a 10 nm silicon transistor using spacer lithography. The device pushed the boundary of what was possible at the time but had major technological problems, including direct tunneling of current through the very thin gate oxide, which meant the transistor effectively couldn’t be shut off.

The team (and the broader field) realized they needed to find other ways to scale the technology and started pursuing new approaches to improving transistor performance, resulting in three key innovations. First they developed innovative ways to introduce strain into the transistors to change the effective mobility and velocity of carriers in the channel. Next they replaced the silicon dioxide with high-k transition metal oxides to overcome reductions in mobility caused by phonon scattering. Finally they changed the planar transistor geometry to a non-planar configuration, referred to as tri-gate or FinFET.

As he described each of these innovations, Datta noted a recurring theme whereby the solution to one challenge would often bring other unexpected benefits through a kind of technological serendipity.

Today the industry is in a mode Datta described as “hyper scaling,” where dimensions of transistors are on the order of Angstroms. He described efforts needed to fabricate the increasingly complex geometries involved and the challenges of thermal management when delivering power to billions of transistors in a single chip.

While advances in transistor performance continue to grow our logic capabilities, Datta noted that we’re now coming up against a memory bottleneck. Conventional computers make data locally available to logic cores by moving it from off-chip DRAM into a local cache (SRAM) that can be accessed with very high internal bandwidth. However, applications like training neural networks require enormous amounts of data that can’t fit in a local cache, creating a bottleneck in how fast the data can be accessed on off-chip memory. Datta discussed his work developing embedded on-chip DRAM, stacking up cache memory directly on the chip instead, which comes with a plethora of technological challenges. He also discussed efforts to reduce data-shuttling needs by performing some logic in the memory itself, again highlighting areas rich with research challenges for young researchers.

Datta identified a list of needs to maintain compute performance gains in the coming decades: accelerated development of materials with tailored properties; monolithic three-dimensional technologies for logic, memory, power delivery, and thermal management; design automation to help assemble mix-and-match technologies; and co-optimization of devices, circuits, systems, and applications for maximal use of hardware resources.

Symposium X—MRS/The Kavli Foundation Frontiers of Materials features lectures aimed at a broad audience to provide meeting attendees with an overview of leading-edge topics.